The present invention relates generally to a programming arrangement for matrices and, more particularly, to an arrangement for programming a matrix which does not require application of higher than normal logic level signals to either the matrix power supply input or the matrix output terminals.
Programmable memory devices are currently programmed by a number of techniques which usually require raising the power supply input, and/or one of several output pins to a level voltage which is substantially higher than normal operational voltage levels. Raising the power supply input voltage dramatically increases current consumption of the device during operation in the programming or editing mode. Raising the voltage level at the output terminals above the normal operational voltage level requires that adequate breakdown protection be provided in the output circuitry. Such protection has an adverse impact upon the AC performance (i.e., the operating speed) of the memory device.
U.S. Pat. No. 4,125,880 to Taylor is a Harris Corporation patent which illustrates a known programming technique of this type. In Taylor, a ten volt signal is applied to output pin 60, causing a zener diode 74 to conduct and transistor 72 to turn on. The power supply terminal V.sub.CC, which is connected to the collectors of the transistors in the matrix, is raised from the normal operating level of 5 volts to a programming level of 12 volts. When a selected memory location is addressed, diode 78 and transistor 72 provide a low impedance current sink for the flow of programming current resulting from the high collector voltage present at the selected memory location. A voltage is applied to chip enable terminal 20 to turn off transistor 52 to prevent programming currents or voltages from damaging output transistor 58.
U.S. Pat. No. 4,276,617 to Le shows another technique for protecting the output network from programming currents. This patent describes a programming logic circuit which is activated by a signal EN to produce low voltages A and B and high voltage C. High voltage C activates transistors 103 and 105 to provide a direct connection between the select logic 40 and the output pin 0, bypassing the sense amplifier. Voltages A and B disable the remainder of the sense amplifiers. Thus, the output circuitry is protected from the programming current which is applied to output terminal 0.
As noted, programming techniques such as those described above consume relatively large amounts of power, dissipate correspondingly large amounts of power in the device, and/or require additional circuitry for protecting output circuits from the high programming voltages and currents. Thus, there exists a need for a new technique of programming a matrix which provides for low power consumption and dissipation during programming and editing functions, and which provides a low AC performance impact.
Accordingly, an object of the present invention is to provide a programming arrangement for a programmable matrix which eliminates the need for breakdown voltage protection on the output pins, thus improving AC performance and eliminating potential AC design limitations.
Another object of the present invention is to provide a programming arrangement which significantly lowers power consumption and dissipation during programming and editing modes.
Still another object of the present invention is to provide a programmable array which does not require a change in the power supply voltage, thus allowing for the use of "in system" programming procedures.
These and other objects of the invention are attained in a programmable matrix having bit addressing inputs, bit outputs, a power supply input, a programming current input, and programming control circuitry which comprises a multi-purpose input pin, a circuit for providing programming current to the programming current input, a bidirectional output buffer, and circuitry for producing a programming enable signal when a higher than normal operating level voltage signal is applied to the multi-purpose input pin. The bidirectional buffer is connected to the bit outputs of the matrix and has at least one buffer output and a control input for receiving the programming enable signal. The buffer provides a path for programming current to flow from a selected bit location in the matrix when a normal operating level pulse is provided at the buffer output while the programming enable signal is present at the control input. The control input of the buffer is isolated from the buffer output terminal by a first switching device. This switching device is responsive to a normal operating level voltage signal, applied to the buffer output, to cause a second switching device in the buffer to provide a path to ground for programming current from a selected bit location. The programming current circuitry may also be provided with a buffer which is responsive to the programming enable signal to control the flow of programming current.
In a preferred embodiment, the multi-purpose input pin is connected to three separate circuits, each responsive to a different voltage level signal. The multi-purpose pin is connected to an operating circuit, such as a chip enable circuit, which is responsive to a normal operating level voltage signal applied to the pin. The pin is also connected to the programming circuitry which produces the programming enable signal in response to a higher than normal voltage level signal applied to the pin. The pin is further connected to the programming current supply and to the programming current input for supplying programming current to the matrix when a programming level voltage (which may be higher than the higher than normal voltage signal) is applied to the pin.
A preferred method of programming the matrix includes the steps of: applying addressing level voltage signals to the bit addressing inputs to select a bit to be programmed; applying a programming level voltage signal to the programming current input; applying a programming enable signal to the control input of the bidirectional buffer; and selectively applying a normal logic level voltage signal to the buffer output to cause the bi-directional buffer to provide a path for programming current to flow from the selected bit.
By connecting the programming current supply to an input pin, the potential for breakdown which exists when the power supply pin or an output pin is raised to a high voltage for programming is essentially eliminated. The proposed technique converts the output pins of the buffer into bidirectional pins that will accept TTL level inputs to initiate programming. These bidirectional pins function as output pins until the output buffer is enabled by a first higher voltage supplied to the multi-purpose input pin. With the first higher voltage present at this input pin, and a second higher voltage applied to this, or another, input pin to supply programming current, the bidirectional pins can be used to trigger the programming event via application of a normal operating level voltage signal.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.